Best Physical Design Training Institute With 100% Placement in Bangalore

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Teacher

Overview

COURSE DESCRIPTION

Upgrade VLSI’s physical design course is designed to give hands on experience in designing complex chip physical design from RTL to GDS by utilizing industry standard EDA tools. Course majorly focuses in improving student skill set from the basics and gradually introduce more complex topics with the help of industry standard live projects. Course material, hand-outs and regular assignments help student to get quick jobs in the semiconductor market. By end of the course you will learn all basics required for interview, physical design flow such from floorplanning, power planning, placement, clock tree synthesis and physical verification.

Upgrade VLSI is top 10 best physical design training institute in India for job oriented physical design training. Our trainers are 15+ years of experienced industry working professionals.

ELIGIBILITY

B.E/B.Tech in EEE, ECE & EIE pursuing or completed.
M.E/M.Tech/M.S in VLSI/Embedded/Any other specialization

MODE OF STUDY

Available in Offline and Online modes.
Daily online classes conducted along with VPN based lab access.

LEARNING OUTCOMES

Get hands-on experience in physical design from RTL to GDSII by executing industry standard live projects.
Gain deep knowledge in chip design concepts such as floorplanning, power planning and building various type of clock trees.
Acquire skill set in Static Timing Analysis and Synthesis.
Learn to verify chip design using all physical verification concepts.
Placement ready with improved softskills and digital basics.

KEY COURSE FEATURES

100% placement and tool support till placement is done.
24×7 tool access through vpn.
Affordable fee and EMI facility.
Industry live projects under the supervision of 15+ experienced trainer.
Course material, hand-outs, quizzes, assignments to assist in learning.

Course Features

Lectures 42
Quizzes 0
Duration 22 weeks
Skill level Beginner
Language English
Students 20
Assessments Yes

Curriculum

Module 1: Basics of Unix/Linux 3
- Lecture1.1
  Introduction and Working knowledge of UNIX/LINUX commands Copy
- Lecture1.2
  File handling skills in UNIX/LINUX Copy
- Lecture1.3
  Introduction to TCL Commands Copy
Module 2: Basics of CMOS 1
- Lecture2.1
  Basics of CMOS Copy
Module 3: Digital Electronics 3
- Lecture3.1
  Binary system and Boolean algebra Copy
- Lecture3.2
  Combinational Circuits Copy
- Lecture3.3
  Sequential circuits – Counter, State machines, Shift registers Copy
Module 4: Introduction to ASIC Design 2
- Lecture4.1
  ASIC Flow Copy
- Lecture4.2
  All Stages Discussion Copy
Module 5: Introduction to Verilog 5
- Lecture5.1
  Basic concepts Copy
- Lecture5.2
  Gate-Level Modeling Copy
- Lecture5.3
  Dataflow Modeling Copy
- Lecture5.4
  Behavioural Modelling Copy
- Lecture5.5
  Tasks and Functions Copy
Module 6: Introduction to DFT 5
- Lecture6.1
  DFT Basics Copy
- Lecture6.2
  Fault Modelling Copy
- Lecture6.3
  Logic and Fault simulation Copy
- Lecture6.4
  SCAN Design Copy
- Lecture6.5
  Introduction to BIST Copy
Module 7: Synthesis 4
- Lecture7.1
  Inputs and Outputs understanding Copy
- Lecture7.2
  Constraints development and understanding Copy
- Lecture7.3
  Optimization techniques (uniqify, preserve, flatten) Copy
- Lecture7.4
  Wireload model, PLE, Physical, Spatial Copy
Module 8: Static Timing Analysis Part – 1 3
Module 9: Static Timing Analysis Part – 2 4
- Lecture9.1
  PLL jitter understanding and uncertainty calculations Copy
- Lecture9.2
  IO budgetting Copy
- Lecture9.3
  Different Timing Modes understanding Copy
- Lecture9.4
  Introduction to ECO Copy
Module 10: Physical Design 6
- Lecture10.1
  Input files, Sanity Checks and IO placement Copy
- Lecture10.2
  Floorplanning and Power planning concepts Copy
- Lecture10.3
  Placement strategies like region, fence, blockages, pading, bump, dont touch, filler gap, DRV optimization, Buffer tree synthesis Copy
- Lecture10.4
  Clock tree synthesis and clock latency calculations Copy
- Lecture10.5
  Routing design and optimization, antenna Effect and Latch up issue Copy
- Lecture10.6
  ECO Timing closure and implementation cycle Copy
Module 11: Physical Design Verification 4
- Lecture11.1
  Design Rule Checks understanding and importance Copy
- Lecture11.2
  Layout Versus Schematic and difference with respect to LEC Copy
- Lecture11.3
  Electrical Rule Checks Copy
- Lecture11.4
  IR Drop analysis – Static and Dynamic Copy
Module 12: Industry standard Project Execution 1
- Lecture12.1
  Industry Standard Physical Design Live Project Copy
Module 13: Mock Interviews & Personality Improvement 1
- Lecture13.1
  Mock Interviews & Personality Improvement Copy

Instructor

Sanjay

Sanjay has 12+ years of rich experience in physical design domain. He worked on complete RTL to GDSII flow of cutting edge technology nodes 7nm, 14nm, 28nm from block level and top level. His work involves floorplanning, power planning, clock tree sysnthesis (CTS), DFM, RC extraction, STA and signal integrity (crosstalk) analysis, Formal and physical verification of complex chip sets such as Modem, Memories, PCIe, PHY.

He is also managing an ASIC Backed Design team from RTL to tapeout/Signoff including managing tools flows and design issues. He is our expert for giving hands-on tool and theory knowledge to students.