ASIC Verification Weekend

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Teacher

Overview

COURSE DESCRIPTION

Upgrade VLSI’s job oriented ASIC Design & Verification weekend online course is designed to give industry standard live experience to a student. Course majorly focuses on giving handson experience in Verilog, System Verilog and UVM using EDA tools. Live projects such as AXI to I2C bridge protocol cover all aspects of design verification using system Verilog and universal verification methodology (UVM). By end of the course student will have all knowledge required to kick-start their career in ASIC verification domain.

Upgrade VLSI is top 10 best ASIC Design and Verification training institute in India for job oriented ASIC Verification training. Our trainers are 15+ years of experienced industry working professionals.

ELIGIBILITY

B.E/B.Tech in EEE, ECE & EIE pursuing or completed.
M.E/M.Tech/M.S in VLSI/Embedded/Any other specialization

MODE OF STUDY

Weekend online classes conducted along with VPN based lab access.

LEARNING OUTCOMES

Get handson experience in System Verilog, UVM and HDL’s by executing industry standard live projects.
Gain deep knowledge in developing Verification Plan, Test Plan, Functional Coverage Plan and Coverage Analysis.
Acquire skill in Regression flow automation.
Complete understanding of ASIC and FPGA design flows.
Placements ready with improved softskills and strong digital basics.

KEY COURSE FEATURES

100% placement and tool support till placement is done.
24×7 tool access through vpn.
Affordable fee and EMI facility.
Industry live projects under the supervision of 15+ experienced trainer.
Course material, hand-outs, quizzes, assignments to assist in learning.

Course Features

Lectures 29
Quizzes 0
Duration 22 weeks
Skill level Beginner
Language English
Students 15
Assessments Yes

Curriculum

Module 1: Basics of Unix/Linux 3
- Lecture1.1
  Introduction and Working knowledge of UNIX/LINUX commands
- Lecture1.2
  UNIX Directory Structures and Unix Commands
- Lecture1.3
  UNIX Shells
Module 2: Advanced Digital Electronics and Digital Logic Designs 4
- Lecture2.1
  Revision of Digital Electronics
- Lecture2.2
  Basics of CMOS Logic Design and Realization of Digital Circuits
- Lecture2.3
  Advanced Arithmetic and Logic Designs
- Lecture2.4
  FPGA Design Flows and Architectures
Module 3: Scripting Languages (Widely Used in Industry) 3
- Lecture3.1
  Basics of PERL
- Lecture3.2
  Basics of TCL
- Lecture3.3
  Introduction to Process Automation using Perl Scripting
Module 4: EDA Tool Introduction 2
- Lecture4.1
  Logic Simulation Tools – Questa Sim
- Lecture4.2
  Logic Synthesis Tools – Xilinx for Synthesis of Design
Module 5: HDLs For Digital Logic Design and Verification 2
- Lecture5.1
  Introduction to HDLs
- Lecture5.2
  Verilog HDL’s
Module 6: Digital Logic Design and Verification using Verilog 1
- Lecture6.1
  Digital Logic Design and Verification using Verilog
Module 7: Mini Project on Verilog 1
- Lecture7.1
  Mini Project on Verilog
Module 8: Introduction to Logic Synthesis 1
- Lecture8.1
  Introduction to Logic Synthesis
Module 9: Design Verification using System Verilog 6
- Lecture9.1
  Introduction to System Verilog
- Lecture9.2
  Introduction to OOPs
- Lecture9.3
  Threads and Mailbox
- Lecture9.4
  Introduction to Callbacks
- Lecture9.5
  Functional Coverage
- Lecture9.6
  Introduction to Assertions
Module 10: Mini Project on System Verilog 1
- Lecture10.1
  Mini Project on System Verilog
Module 11: Design Verification using UVM 1
- Lecture11.1
  Design Verification using UVM
Module 12: Mini Project on UVM 1
- Lecture12.1
  Mini Project on UVM
Module 13: UVM-RAL 1
- Lecture13.1
  UVM environment using register layer of UVM
Module 14: Developing Verification Plan, Test Plan, Functional Coverage Plan and Coverage Analysis 1
- Lecture14.1
  Major project on AXI-I2C/SPI bridge covering the SV-UVM features
Module 15: Mock Interviews & Personality Improvement 1
- Lecture15.1
  Mock Interviews & Personality Improvement

Instructor

Sharath

Sharath is having 15+ years of experience in CPU Design and Verification, Universal Verification Methodology (UVM), IP/SOC verification, He worked on protocols such as DDR5, PCIe, USB, SATA, Ethernet IP and Sub-System level Verification.

Having experience in writing/analyzing coverage matrix such as functional coverage, code coverage and SVA assertions. Worked and lead across functional Design and Verification teams. Experience in both ARM as well as ARC Architectures. Having working experience with tools modelsim, Questasim ,VCS, Simvision, Dve, Debussy ,NCSim, Verdi. He is our expert for providing hands-on experience to our students.