- Module 1: Basics of Unix/Linux 3
- Introduction and Working knowledge of UNIX/LINUX commands CopyLecture1.1
- UNIX Directory Structures and Unix CommandsLecture1.2
- UNIX ShellsLecture1.3
- Module 2: Advanced Digital Electronics and Digital Logic Designs 4
- Revision of Digital ElectronicsLecture2.1
- Basics of CMOS Logic Design and Realization of Digital CircuitsLecture2.2
- Advanced Arithmetic and Logic DesignsLecture2.3
- FPGA Design Flows and ArchitecturesLecture2.4
- Module 3: Scripting Languages (Widely Used in Industry) 3
- Basics of PERLLecture3.1
- Basics of TCLLecture3.2
- Introduction to Process Automation using Perl ScriptingLecture3.3
- Module 4: EDA Tool Introduction 2
- Logic Simulation Tools – Questa SimLecture4.1
- Logic Synthesis Tools – Xilinx for Synthesis of DesignLecture4.2
- Module 5: HDLs For Digital Logic Design and Verification 2
- Introduction to HDLsLecture5.1
- Verilog HDL’sLecture5.2
- Module 6: Digital Logic Design and Verification using Verilog 1
- Module 7: Mini Project on Verilog 1
- Mini Project on VerilogLecture7.1
- Module 8: Introduction to Logic Synthesis 1
- Introduction to Logic SynthesisLecture8.1
- Module 9: Design Verification using System Verilog 6
- Introduction to System VerilogLecture9.1
- Introduction to OOPsLecture9.2
- Threads and MailboxLecture9.3
- Introduction to CallbacksLecture9.4
- Functional CoverageLecture9.5
- Introduction to AssertionsLecture9.6
- Module 10: Mini Project on System Verilog 1
- Mini Project on System VerilogLecture10.1
- Module 11: Design Verification using UVM 1
- Design Verification using UVMLecture11.1
- Module 12: Mini Project on UVM 1
- Mini Project on UVMLecture12.1
- Module 13: UVM-RAL 1
- UVM environment using register layer of UVMLecture13.1
- Module 14: Developing Verification Plan, Test Plan, Functional Coverage Plan and Coverage Analysis 1
- Module 15: Mock Interviews & Personality Improvement 1
- Mock Interviews & Personality ImprovementLecture15.1
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Major project on AXI-I2C/SPI bridge covering the SV-UVM features
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