- Module 1: Basics of Unix/Linux 4
- Introduction and working knowledge of Unix/Linux commands CopyLecture1.1
- File handling skills in UNIX/LINUX CopyLecture1.2
- Introduction to TCL commands CopyLecture1.3
- testLecture1.4
- Module 2: Digital Electronics 3
- Binary system and Boolean algebra CopyLecture2.1
- Combinbational Circuits CopyLecture2.2
- Sequential circuits – Counters, state machines, shift registers CopyLecture2.3
- Module 3: Introduction to ASIC Design 2
- ASIC Flow CopyLecture3.1
- All Satges Discussion CopyLecture3.2
- Module 4: Introduction to Verilog 5
- Basic Concepts CopyLecture4.1
- Gate – Level Modeling CopyLecture4.2
- Dataflow Modeling CopyLecture4.3
- Behavioural Modeling CopyLecture4.4
- Tasks and Functions CopyLecture4.5
- Module 5: Design For Test 8
- Need for Testing CopyLecture5.1
- Design for Test CopyLecture5.2
- DFT-Digital Design CopyLecture5.3
- ATPG-Common Terminology CopyLecture5.4
- ATPG CopyLecture5.5
- Scan ATPG & Fault Simulation CopyLecture5.6
- Scan Design Rules CopyLecture5.7
- Scan Test for Transition Delay CopyLecture5.8
- Module 6: DFT-BIST 5
- BIST CopyLecture6.1
- MBIST CopyLecture6.2
- MBIST control modes CopyLecture6.3
- LBIST CopyLecture6.4
- Boundary Scan CopyLecture6.5
- Module 7: DFT Compiler & Tetramax 8
- Overview CopyLecture7.1
- Flows Supported by DFT Compiler CopyLecture7.2
- Scan Insertion Flow CopyLecture7.3
- DFT Compiler Flow and supported Commands CopyLecture7.4
- Tetramax Flow for ATPG CopyLecture7.5
- Steps involved in ATPG mode CopyLecture7.6
- ATPG models targeted by Tetramax CopyLecture7.7
- ATPG Simulations CopyLecture7.8
- Module 8: Industry standard Project Execution 1
- Industry Standard DFT Live Project CopyLecture8.1
- Module 9: Mock Interviews & Personality Improvement 1
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