- Module 1: Basics of Unix/Linux 3
- Introduction and Working knowledge of UNIX/LINUX commandsLecture1.1
- File handling skills in UNIX/LINUXLecture1.2
- Introduction to TCL CommandsLecture1.3
- Module 2: Basics of CMOS 1
- Basics of CMOSLecture2.1
- Module 3: Digital Electronics 3
- Binary system and Boolean algebraLecture3.1
- Combinational CircuitsLecture3.2
- Sequential circuits – Counter, State machines, Shift registersLecture3.3
- Module 4: Introduction to ASIC Design 2
- ASIC FlowLecture4.1
- All Stages DiscussionLecture4.2
- Module 5: Introduction to Verilog 5
- Basic conceptsLecture5.1
- Gate-Level ModelingLecture5.2
- Dataflow ModelingLecture5.3
- Behavioural ModellingLecture5.4
- Tasks and FunctionsLecture5.5
- Module 6: Introduction to DFT 5
- DFT BasicsLecture6.1
- Fault ModellingLecture6.2
- Logic and Fault simulationLecture6.3
- SCAN DesignLecture6.4
- Introduction to BISTLecture6.5
- Module 7: Synthesis 4
- Inputs and Outputs understandingLecture7.1
- Constraints development and understandingLecture7.2
- Optimization techniques (uniqify, preserve, flatten)Lecture7.3
- Wireload model, PLE, Physical, SpatialLecture7.4
- Module 8: Static Timing Analysis Part – 1 3
- Basic understanding of transition/slew, capacitance, leakage power, internal power, On-Chip-Variation (derate, AOCV, LVF)Lecture8.1
- Library file difference NLDM, CCS, ECSM, LVFLecture8.2
- Timing concepts understanding such as setup, hold, recovery, removal, pulse_width, clock gating checkLecture8.3
- Module 9: Static Timing Analysis Part – 2 4
- PLL jitter understanding and uncertainty calculationsLecture9.1
- IO budgettingLecture9.2
- Different Timing Modes understandingLecture9.3
- Introduction to ECOLecture9.4
- Module 10: Physical Design 6
- Input files, Sanity Checks and IO placementLecture10.1
- Floorplanning and Power planning conceptsLecture10.2
- Placement strategies like region, fence, blockages, pading, bump, dont touch, filler gap, DRV optimization, Buffer tree synthesisLecture10.3
- Clock tree synthesis and clock latency calculationsLecture10.4
- Routing design and optimization, antenna Effect and Latch up issueLecture10.5
- ECO Timing closure and implementation cycleLecture10.6
- Module 11: Physical Design Verification 4
- Design Rule Checks understanding and importanceLecture11.1
- Layout Versus Schematic and difference with respect to LECLecture11.2
- Electrical Rule ChecksLecture11.3
- IR Drop analysis – Static and DynamicLecture11.4
- Module 12: Industry standard Project Execution 1
- Industry Standard Physical Design Live ProjectLecture12.1
- Module 13: Mock Interviews & Personality Improvement 1
- Mock Interviews & Personality ImprovementLecture13.1
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