Sanjay
Sanjay has 12+ years of rich experience in physical design domain. He worked on complete RTL to GDSII flow of cutting edge technology nodes 7nm, 14nm, 28nm from block level and top level. His work involves floorplanning, power planning, clock tree sysnthesis (CTS), DFM, RC extraction, STA and signal integrity (crosstalk) analysis, Formal and physical verification of complex chip sets such as Modem, Memories, PCIe, PHY.
He is also managing an ASIC Backed Design team from RTL to tapeout/Signoff including managing tools flows and design issues. He is our expert for giving hands-on tool and theory knowledge to students.